Working Paper: NBER ID: w29936
Authors: Bhagath Cheela; Andr Dehon; Jess Fernández-Villaverde; Alessandro Peri
Abstract: We show how to use field-programmable gate arrays (FPGAs) and their associated high-level synthesis (HLS) compilers to solve heterogeneous agent models with incomplete markets and aggregate uncertainty (Krusell and Smith, 1998). We document that the acceleration delivered by one single FPGA is comparable to that provided by using 74 CPU cores in a conventional cluster. We describe how to achieve multiple acceleration opportunities—pipeline, data-level parallelism, and data precision—with minimal modification of the C code written for a traditional sequential processor, which we then deploy on FPGAs easily available at Amazon Web Services. We quantify the speedup and cost of these accelerations. Our paper is the first step toward a new field, electrical engineering economics, focused on designing computational accelerators for economics to tackle challenging quantitative models.
Keywords: No keywords provided
JEL Codes: C60; C63; C88; D52
Edges that are evidenced by causal inference methods are in orange, and the rest are in light blue.
| Cause | Effect |
|---|---|
| FPGA deployment (L63) | computational speed (C63) |
| 8 FPGAs (L63) | solving 1200 economies faster than 1 CPU core (D58) |
| 8 FPGAs (L63) | solving 1200 economies faster than 48 CPU cores (D58) |
| increasing FPGA usage (C88) | computational efficiency (C63) |
| pipelining, data-level parallelism, tuning data precision (C55) | speedup (C69) |