Working Paper: CEPR ID: DP17183
Authors: Bhagath Cheela; Andre Dehon; Jess Fernández Villaverde; Alessandro Peri
Abstract: We show how to use field-programmable gate arrays (FPGAs) and their associated high-level synthesis (HLS) compilers to solve heterogeneous agent models with incomplete markets and aggregate uncertainty (Krusell and Smith, 1998). We document that the acceleration delivered by one single FPGA is comparable to that provided by using 74 CPU cores in a conventional cluster. We describe how to achieve multiple acceleration opportunities -pipeline, data-level parallelism, and data precision- with minimal modification of the C code written for a traditional sequential processor, which we then deploy on FPGAs easily available at Amazon Web Services. We quantify the speedup and cost of these accelerations. Our paper is the first step toward a new field, electrical engineering economics, focused on designing computational accelerators for economics to tackle challenging quantitative models.
Keywords: FPGA acceleration; FPGA HLS compilers; heterogeneous agents; electrical engineering economics
JEL Codes: C6; C63; C88; D52
Edges that are evidenced by causal inference methods are in orange, and the rest are in light blue.
| Cause | Effect |
|---|---|
| FPGA implementation (C88) | computational speed (C63) |
| FPGA implementation (C88) | execution time reduction (C41) |
| one FPGA (L63) | solving economies faster than 48 CPU cores (E19) |
| FPGA implementation (C88) | energy savings (Q41) |
| pipelining and data-level parallelism (C55) | performance improvements (D29) |